// cookbook

Peripheral cookbook.

One page per peripheral. Each cookbook lists the register-level recipe, the assembly call sequence, the gotchas we hit on real silicon, and a working demo. These are the references that grew out of debugging the SDK against hardware.

// bring-up

Boot - bootrom -> `_reset` -> `main`

This document covers the early-boot path in src/startup.S and the two linker layouts in link/. If you're chasing a new bring-up failure, the [Debugging boot hangs](#debugging-boot-hangs) section at the bottom is the entry point.

A layered, customer-flavorable boot chain for the RP2350. The stack:

M2 - clocks / reset / power

This document covers the RP2350 clock-tree configuration installed by src/main.S (the production firmware) and examples/clocks_demo.S (a standalone fixture).

// calling conventions

ticktrace calling conventions

All drivers in src/ follow AAPCS (ARM Architecture Procedure Call Standard), because they need to be callable from each other and from user code without surprises. This page documents what that means in practice and gives a worked example f

Opt-in C ABI on top of the ticktrace core. Write your application in C; the drivers stay in asm. AAPCS makes the call boundary free.

Opt-in Rust toolchain on top of the ticktrace core. Write #![no_std] Rust applications that call our asm drivers via extern "C". AAPCS makes the bridge free; the work is wiring cargo to find our static archive and use our linker script.

Rust ecosystem via embedded-hal

The Rust bridge ([docs/rust_bridge.md](rust_bridge.md)) gets you unsafe extern "C" access to every ticktrace driver. **This page is about the layer above it**: embedded-hal trait implementations so that thousands of existing Rust driver cra

// gpio & timing

M3-A: GPIO / PADS

Full RP2350 GPIO subsystem coverage: 48 user GPIOs in IO_BANK0 + 6 QSPI pins in IO_QSPI, all atomic-aliased and per-pad configurable. This is the "complete" GPIO driver; it supersedes the v0.1 single-pin LED helpers, which remain as thin ba

M3-B - TIMER0 / TIMER1 / SysTick

This document covers the RP2350 wall-clock timers and the Cortex-M33 SysTick reload counter, as implemented by src/timer.S, src/systick.S, and the NVIC helpers in src/nvic.S.

src/nvic.S is the minimal Cortex-M33 NVIC wrapper layer. It exists because the NVIC has six different register banks for what is conceptually "set/clear/enable/pending/priority for IRQ N", and forgetting which is which is a great way to sp

// comms

M4-E - UART (PL011)

This document covers the RP2350 UART driver in src/uart.S and the three end-to-end demos in examples/uart_*.S.

Two-wire serial bus controller. RP2350 has **two instances** of the Synopsys DesignWare DW_apb_i2c (same IP block as the RP2040). Both can operate as master or slave at Standard (100 kHz), Fast (400 kHz) or Fast+ (1 MHz) speeds with 7- or

M4-G - SPI (PL022) controllers

This document covers the RP2350 SPI driver in src/spi.S and the three end-to-end demos in examples/spi_*.S.

USB device controller (M4-H)

src/usb.S is the ticktrace USB device-mode driver, plus a minimal CDC-ACM class layer. Plug a Pico 2 running usb_cdc_echo_demo.uf2 into a host and /dev/ttyACM0 will appear; bytes you send round-trip back as echoes.

// throughput

M3-C - DMA controller

This document covers the RP2350 DMA controller driver in src/dma.S and the three end-to-end demos in examples/dma_*.S.

Pulse-width modulation peripheral. RP2350 has **12 slices**, each with two output channels (A and B), giving 24 PWM-capable outputs. Datasheet reference: RP2350 sec 12.5.

RP2350 has an 8-channel, 12-bit SAR ADC (RP2040 had 4 channels). Sample rate up to 500 kS/s.

RP2350 has **3 PIO blocks** (PIO0/PIO1/PIO2), up from 2 on RP2040. Each is 4 state machines × 32 instructions of program memory + per-SM 4-deep TX/RX FIFOs. This page covers the controller-side driver. The PIO assembly language itself (the

// crypto / random

RP2350 ships a hardware SHA-256 engine. Push 64-byte message blocks into a write-only FIFO; pull a 256-bit digest out at the end. The hardware does *not* pad; that's the firmware's job.

True random number generator, new on RP2350 (RP2040 had none). Built on an ARM CryptoCell-312 RNG block: a ring-oscillator entropy source feeds a 192-bit Entropy Holding Register (EHR) which the firmware drains as six 32-bit words at a time

// concurrency

Scheduler: NVIC-priority kernel (QV-style)

A 200-LOC asm scheduler that uses the Cortex-M33 NVIC as its dispatch engine. Inspired by Quantum Leaps' QV (Vanilla) kernel; the architecture is the same; this is a from-scratch asm implementation.

SPSC byte queue

Lock-free single-producer, single-consumer byte queue. The canonical use is "hardware ISR pushes; soft task pops"; the SPSC role guarantees no locks are needed.

Per-task DWT cycle accounting

Opt-in cycle-accounting layer on top of src/sched.S. When you create a task with task_create_traced instead of task_create, a tiny trampoline samples DWT.CYCCNT around every invocation and updates three per-task counters.

// trace & test

Trace (CoreSight DWT/ITM/TPIU/ETM)

For T4 hardware debugging. Cortex-M33 ships with four CoreSight components that together give you on-target cycle counting, printf-over-SWO, and full instruction trace.

Benchmarking ticktrace vs pico-sdk

This is how we put numbers on "every cycle matters". The benchmark suite lives in benchmarks/, builds on both sides with the same shape, and emits parseable BENCH … lines so a host script can tabulate results without any per-bench glue.

// apps & studio

Building apps with ticktrace

This is the practical companion to docs/calling.md. That one explains the contract; this one walks you through using it. By the end you'll know how to write your own Pico 2 app, compose it with the SDK drivers, build a UF2, and (when someth

A sibling product to the ticktrace SDK that lets users pick a target, toggle peripherals, build, and flash without touching make or picotool. Studio lives in studio/ as its own Go module and consumes the parent SDK by relative paths: module